1. Field of the Invention
The present invention relates to an electronic component built-in substrate in which an electronic component such as a semiconductor chip, or the like is built, and a method of manufacturing the same.
2. Description of the Related Art
In the prior art, there are various electronic component built-in substrates in which an electronic component such as a semiconductor chip, or the like is built. In such electronic component built-in substrates, a semiconductor chip is mounted on a wiring substrate and then the semiconductor chip is embedded in an insulating layer, and then vias reaching a connection pad of the semiconductor chip respectively are opened by the laser or the photolithography and then the semiconductor chip is connected electrically to the wiring substrate via the vias (Patent Literature 1 (Patent Application Publication (KOKAI) 2004-179288) and Patent Literature 2 (Patent Application Publication (KOKAI) 2002-246757)).
In Patent Literature 3 (Patent Application Publication (KOKAI) 2001-332643), the method of mounting a semiconductor chip in which copper posts are formed on a wiring substrate, then embedding the semiconductor chip in an insulating layer, and then exposing the copper posts by polishing the insulating layer is set forth.
Also, in Patent Literature 4 (Patent Application Publication (KOKAI) 2000-323645), it is set forth that a semiconductor element is mounted on wiring layers of a wiring substrate to direct its function surface to the upper side, then an insulating layer whose thickness is substantially equal to the semiconductor element is formed such that the function surface of the semiconductor element is exposed, and then connection patterns extended from an electrode terminal of the semiconductor element onto the insulating layer respectively are formed.
Also, in Patent Literature 5 (Patent Application Publication (KOKAI) 2004-47725), it is set forth that a rewiring circuit is formed by pasting a conductor layer built-in dry film onto a semiconductor wafer, on which stud bumps are formed, to make the stud bumps penetrate a conductor layer, then exposing the stud bumps by peeling off a base film, and then forming an electroplating copper layer and patterning the layer.
As explained in the column of related art described later, in the case of the method of forming the via holes in the insulating layer in which the semiconductor chip is embedded by the laser, a laser stop layer for protecting the semiconductor chip from the laser must be formed to be made patterns on the connection pads of the semiconductor chip. In this case, such a problem exists that, since the stop layer is formed via complicated steps in a state of a semiconductor wafer, various manufacturing equipments for wafer processes are needed on the mounting line to cause an increase in cost.
Also, in the method of exposing the copper posts of the semiconductor chip by polishing the insulating layer (Patent Literature 3), since the copper posts must be formed similarly in a state of the semiconductor wafer, it is feared that an increase in cost is caused.